1. Field of the Invention
This invention relates generally to computers. More particularly, it relates to interrupt controllers for controlling interrupts in a computer.
2. Description of the Related Art
A computer is a machine that essentially does three things. First, it accepts input. Second, it processes the input according to a prescribed set of rules. Third, it produces as output the results of processing the input according to the prescribed set of rules.
To perform these tasks, a computer, in general, includes: an input device, such as a keyboard, that accepts input; and output device, such as a printer or video display, that outputs the results; and a processor, such as a central processing unit (CPU), that does the processing. In present-day personal computers, the CPU might be a microprocessor. Additionally, the computer might have memory. Such memory might be used by the processor to store data. Or the memory might be used to store computer instructions, which instructions were put into the memory in the form of microcode.
While the computer is operating and the processor is processing the input previously received by the computer according to the prescribed set of rules, the processor might receive a request for attention. For example, the processor might receive a request from the keyboard to accept new input. Such a request for attention is called an interrupt.
In general, when the processor receives an interrupt it suspends its current operations, saves the status of its work, and transfers control to a special routine which contains the instructions for dealing with the particular situation that caused the interrupt. Interrupts might be generated by various hardware devices to request service or to report problems, or by the processor itself in response to program errors or requests for operating system services. Interrupts are the processor's way of communicating with the other elements that make up the computer system. A hierarchy of interrupt priorities determines which interrupt request will be handled first, if more than one request has been made. Particular programs can temporarily disable some interrupts, when the program needs the full attention of the processor to complete a particular task.
In general, an interrupt can be considered a feature of a computer that permits the execution of one program to be interrupted in order to execute another program. That other program might be a special program that is executed when a specific interrupt occurs, sometimes called an interrupt handler. Interrupts from different causes have different handlers to carry out the corresponding tasks, such as updating the system clock or reading the keyboard. A table stored in memory contains pointers, sometimes called address vectors, that direct the processor to the various interrupt handlers. Programmers can create interrupt handlers to replace or supplement existing handlers. Alternatively, that other program might be one that takes place only when requested by means of an interrupt, sometimes called an interrupt-driven process. After the required task has been completed, the CPU is then free to perform other tasks until the next interrupt occurs. Interrupt driven processors sometimes are used to respond to such events as a floppy-disk drive having become ready to transfer data.
In general, computers include a hardware line, sometimes called an interrupt request line, over which devices such as a keyboard or a disk drive can send interrupts to the CPU. Such interrupt request lines are built into the computer's internal hardware, and are assigned different levels of priority so that the CPU can determine the sources and relative importance of incoming service requests.
The manner in which a particular computer deals with interrupts, is determined by the computer's interrupt controller. Each interrupt has a characteristic that permits the interrupt controller to recognize it as an interrupt. One such characteristic is the interrupt's trigger mode. In general, there are two trigger modes, edge-triggered and level-triggered. For an edge-triggered interrupt, the interrupt controller recognizes a positive-going edge of a signal from an interrupt source as a valid interrupt request; for a level-triggered interrupt, the interrupt controller recognizes a static high-level of a signal from an interrupt source as a valid interrupt request.
In certain sophisticated modern microprocessors, such as the PentiumPRO.TM. microprocessor manufactured by Intel, an advanced programmable interrupt controller is included. The advanced programmable interrupt controller of this prior art processor, referred to as APIC, includes an APIC Input/Output (I/O) module that receives system interrupt requests from I/O devices, and routes them to the local APIC modules that are contained in the processor. A three-wire APIC bus connects all of these devices together. The APIC bus carries messages between the APIC I/O module and the local APIC modules contained in the processor. Each processor also has two local interrupt pins, called LINT0 and LINT1, for devices connected externally to the local processor.
When the prior art APIC I/O module sends an interrupt request over the APIC bus, all local APIC modules evaluate the information transferred over the APIC bus. The local APIC module that is being targeted recognizes, accepts, and services the interrupt request.
When the interrupt is accepted in this prior art device, the bit in a trigger mode register corresponding to the interrupt's vector number is made to reflect whether the interrupt is an edge-triggered interrupt or a level-triggered interrupt. The trigger mode register in this prior art device is a 256-bit register, and is used to keep track of the trigger mode of each interrupt. The software programmer may program the interrupt controller's internal registers to recognize either an edge-triggered interrupt or a level-triggered interrupt for each interrupt source.
Edge-triggered interrupt inputs support only a single interrupt source device being connected to a given interrupt input to the I/O APIC. When an interrupt is triggered, the prior art I/O APIC sends an interrupt request over the APIC bus. After the interrupt request is delivered, the I/O APIC automatically clears its interrupt pending bit and is ready to recognize another edge-triggered interrupt from the same interrupt source.
During the interrupt service routine, the programmer of this prior art device clears the interrupt pending bit within the interrupt source device. This notifies the device that the current interrupt is being serviced, and that another interrupt request can be issued. At the end of the interrupt service routine, the programmer performs an end of interrupt command by writing all zero's to the local APIC's end of interrupt register, thereby enabling other pending interrupts to be serviced. This causes the highest-priority interrupt request in the local interrupt service register to be cleared, preventing it from being serviced again.
Level-triggered interrupts permit more than one interrupt source device to share a single interrupt line. When an end of interrupt command is performed by a level-triggered interrupt service routine, the prior art local APIC must broadcast an end of interrupt message to the I/O APIC. The end of interrupt message contains the vector of the level-triggered interrupt just serviced. If the interrupt input corresponding to the end of interrupt vector is still asserted, the I/O APIC recognizes that another device that shares the same interrupt line is requesting service, and transfers another interrupt request over the APIC bus. The I/O APIC cannot detect whether the interrupt input remains asserted because the device that triggered the initial request has yet to be serviced, or because another device is asserting an interrupt request. Consequently, interrupt servicing continues until at some point in time the level on the interrupt line goes inactive and the I/O APIC sends a de-assert message that clears the interrupt pending condition.
The 256-bit trigger mode register of this prior art device keeps track of, and identifies if, a pending interrupt is edge-triggered or level-triggered. An edge-triggered interrupt implies one interrupt invocation per a particular polarity edge; a level-triggered interrupt implies continuous interrupt invocation as long as the static level is present, and thus there may be more than one interrupt invocation.
In processors more advanced and faster than the PentiumPRO.TM., the above scheme in which the APIC must broadcast a de-assert message would result in multiple ghost interrupts, because of the long time it would take for the clear message to go through the various system interface buffers of the microprocessor.
The present invention provides a streamline advanced programmable interrupt controller (SAPIC) that eliminates the need for a trigger mode register. In the present invention, software is responsible in level-triggered interrupt processing to communicate with the input/output system. Thus the knowledge of whether an interrupt is edge-triggered or level-triggered is not needed in hardware. As a result, the portion of the chip formally devoted to a trigger mode register can be used to implement more intelligent logic, thereby giving the chip maker a greater return on investment, and permitting the system to operate at a high speed without the problem of multiple ghost interrupts.